A storage device that has recently come to be used as a storage of a portable device handling audio data and video data, is equipped with a nonvolatile memory such as a flash memory that is updatable, highly portable, and does not require battery backup, and the like.
FIG. 1 is a block diagram showing the structure of a memory card that is an existing nonvolatile storage device.
A memory card 300, which is a device for storing data, being connected to a host apparatus 200 such as a personal computer and a digital camera, includes a controller 310 and a flash memory 320. The host apparatus 200 writes and reads data to and from the memory card 300, by use of a card control signal and a card data signal. Such card control signal and card data signal are inputted/outputted between the host apparatus 200 and the controller 310 inside the memory card 300.
Regarding data writing and reading performed between the controller 310 and the flash memory 320, the controller 310 writes and reads data to and from the flash memory 320 by use of the memory control signal and memory data signal. Note that the flash memory 320 connected to the controller 310 does not have to be one chip, and therefore that plural chips may be connected to the controller 310.
FIG. 2 is a block diagram showing the configuration of the controller 310.
The controller 310 is comprised of an MPU 311, a page RAM 312, an address conversion table 313, and an erase block table 314.
The MPU 311 has an overall control over the controller 310, as well as controlling the data erasure from, data writing to, and data reading from the flash memory 320. The page RAM 312 is a volatile memory for temporarily storing data handled between the host apparatus 200 and the flash memory 320. The address conversion table 313 is a table for making a conversion between a host apparatus 200-specified address of data that is written to the flash memory 320 and a physical address in the flash memory 320. The erase block table 314 is a table that indicates, on a physical address basis, whether physical blocks in the flash memory 320 have already been erased or written. Information stored in the address conversion table 313 and the erase block table 314 is generated by reading out data of all the physical blocks in the flash memory 320 at the power-on time.
FIG. 3 is a block diagram showing the configuration of the flash memory 320.
The flash memory 320 is comprised of a page register 321, a memory cell array 323, a row decoder 324, and a command decoder 325.
The memory cell array 323 is made up of all the memory cells contained in one chip of the flash memory 320. Memory cells constitute a page in units in which reading and writing can be performed simultaneously. Furthermore, a plurality of pages make up a physical block 322 that is an erasure unit. The page register 321 has the capacity equivalent to pages of memory cells, and holds write data to be inputted from the controller 310 and read data to be read out from memory cells. The row decoder 324 selects a page specified by the controller 310 at the time of data reading and writing, whereas it selects a physical block 322 specified by the controller 310 at the time of erasing data. The command decoder 325 executes a command from the controller 310 that is sent as a memory control signal.
FIG. 4 is a schematic diagram showing example correspondence among data elements stored in the address conversion table 313, the erase block table 314, and the flash memory 320.
Data in address 0 described in the address conversion table 313 is a physical address that corresponds to logical address 0. Since such data is “0001” in an example illustrated in FIG. 4(a), it indicates that data in logical address 0 is written in physical address 1 in the flash memory 320. Meanwhile, “FFFF” indicating a physical address that corresponds to logical address 1 is an invalid value that means that there is no data in logical address 1. Here, “invalid value” is an arbitrary value that indicates invalidity and that is defined as invalid under the address conversion rule. An example of such value is a fixed value “0” and the maximum value “65535” in the case of 16-bit data. Furthermore, since data in address 2 in the address conversion table 313 is “0002”, it indicates that data in logical address 2 is written in physical address 2 in the flash memory 320.
Meanwhile, the erase block table 314 shows the state of the respective physical blocks in the flash memory 320. The erase block table 314 holds, as address values, values that correspond to the respective physical addresses in the flash memory 320, and holds, as data values, whether the respective physical blocks in the flash memory 320 have already been erased or written. For example, the erase block table 314 holds the value 1 when a physical block has already been erased, whereas it holds the value 0 when a physical block has already been written. Stated another way, data in address 0 in the erase block table 314 indicates whether a physical block corresponding to physical address 0 in the flash memory 320 has already been erased/written. Since such data is “1” in an example illustrated in FIG. 4(a), it indicates that the physical block corresponding to physical address 0 has already been erased. Similarly, since each data in addresses 1 and 2 in the erase block table 314 is “0”, it indicates that the physical blocks corresponding to the respective physical addresses 1 and 2 in the flash memory 320 have already been written.
Next, a description is given of the operation to be performed when data in the existing memory card 300 with the above structure is updated by the host apparatus 200. FIG. 5 is a timing chart showing a write operation to be performed in such case, whereas FIG. 6 Is a timing chart showing an erase operation to be performed in such case. In the respective timing charts shown in FIGS. 5 and 6, upper signals are the card control signal and card data signal shown in FIG. 1, indicating that data is inputted from the host apparatus 200 to the memory card 300. Middle signals are the memory control signal and memory data signal shown in FIG. 3, indicating that data is inputted from the controller 310 to the flash memory 320. A lower signal is a memory control signal, indicating that data is outputted from the flash memory 320 to the controller 310. Here, a description is given for the case as an example where data in logical address 0 in the memory card 300 is updated, in the state shown in FIG. 4(a).
First, the host apparatus 200 sends, to the memory card 300, a write command 401 for logical address 0 as the card control signal at time t421, and starts transferring the write data as the card data signal at time t422. Such write data is to be stored into the page RAM 312 of the controller 310 in the memory card 300.
Upon receipt of the write command 401 from the host apparatus 200, the controller 310 searches the erase block table 314 for an already erased physical block 322 to which it is possible to write the data. The controller 310 detects from the erase block table 314 that a physical block in physical address 0 is an already erased physical block 322.
After the data transfer from the host apparatus 200 is finished, the controller 310 sends a write address specification command 403 for this data at time t423, so as to indicate the flash memory 320 that the write address is to be inputted thereafter. The command decoder 325 decodes the write address specification command 403, and controls the row decoder 324 to make it obtain the address to be inputted thereafter.
The controller 310 sends a write address 404 to the flash memory 320 at time t424. The row decoder 324 obtains the inputted write address, and selects a specified page so that the data can be written to it. Next, the command decoder 325 recognizes that the write address has been obtained, and controls the page register 321 to obtain the write address to be inputted thereafter.
Next, the controller 310 starts transferring the write data 405 from the page RAM 312 to the flash memory 320 at time t425. The command decoder 325 stores the inputted write data into the page register 321.
Then, the controller 310 sends a write execute command 406 to the flash memory 320 at time t427.
In response to this, the command decoder 325 starts, at time t427, writing the data stored in the page register 321 to memory cells of a page selected by the row decoder 324. At the same time, the command decoder 325 sends, to the controller 310, a write busy 407 as the memory control signal indicating that writing is ongoing. A period defined as the write busy 407 indicates that no data shall be allowed to be newly read out, written, or erased during such period. This is because the command decoder 325 does not allow any commands to be inputted from the controller 310 for the reason that the same page that is subject to writing needs to remain selected by the row decoder 324 while such writing is taking place.
According to a general specification, “erase” and “write” operations to be performed on the flash memory 320 complete separately and therefore no command is to be written while writing and erasure are in busy state (e.g. NH29W12811T datasheet of Hitachi Ltd.)
Next, after the write operation to the page is finished at time t428, the command decoder 325 releases the write busy 407 of the memory control signal. From then on, it is possible for commands to be inputted from the controller 310.
After this, the controller 310 writes, to the other pages of the physical block 322 to which the above writing has been performed, data transferred from the host apparatus 200 in the above-described manner.
After the data writing is finished as in the above manner, the controller 310 obtains, from the address conversion table 313, a physical block in which the data in logical address 0 subject to the writing, was originally written. Since data in address 0 in the address conversion table 313 is “0001” in an example shown in FIG. 4(a), the physical block corresponding to physical address 1 is the location where the old data was written.
Then, in order to erase the old data which became invalid due to the writing performed this time, the controller 310, as shown in FIG. 6, sends an erase address specification command 411 for the physical block 322 corresponding to physical address 1 at time t431, so as to indicate the flash memory 320 that the erase address is to be inputted thereafter. The command decoder 325 decodes the erase address specification command 411, and controls the row decoder 324 to obtain the address to be inputted thereafter.
The controller 310 sends an erase address 412 to the flash memory 320 at time t432. The row decoder 324 obtains the inputted erase address, and selects a specified physical block 322 so that the data can be erased.
Next, the controller 310 sends an erase execute command 413 to the flash memory 320 at time t433.
In response to this, the command decoder 325 starts, at time t434, erasing the physical block 322 selected by the row decoder 324. At the same time, the command decoder 325 sends, to the controller 310, an erase busy 414 as the memory control signal indicating that erasure is ongoing. A period defined as the erase busy 414 indicates that no data shall be allowed to be newly read out, written, or erased during such period, as in the case of writing.
Next, after the erase operation on the physical block 322 is finished at time t435, the command decoder 325 releases the erase busy 414 of the memory control signal.
Then, the MPU 311 of the controller 310 updates the address conversion table 313 and erase block table 314. FIG. 4(b) is a schematic diagram showing the state changed from the state shown in FIG. 4(a) by updating the data in logical address 0.
More specifically, since physical block 322 to which the writing was performed this time is in address 0, the MPU 311 updates the data in address 0 in the erase block table 314 to “0” indicating that the block has already been written. Moreover, as shown in FIG. 4(b), the MPU 311 also updates the value of address 0 in the address conversion table 313 to “0000” that indicates the physical address of the physical block 322 to which the writing has performed this time. Furthermore, since the physical block 322 which was erased this time is in address 1, the MPU 311 updates the data in address 1 in the erase block table 314 to “1” indicating that the block has already been erased, as shown in FIG. 4(b).
Data in the memory card 300 is updated by the host apparatus 200, as in the above-described manner.
Note that in FIGS. 5 and 6, although time widths are represented differently from the actual times for simplification purposes, it actually takes a few ms until an erase busy 414 and a write busy 407 end (e.g. according to NH29W12811T data sheet of Hitachi Ltd., erase busy time is 1 ms and write busy time is 2.5 ms). Furthermore, it takes a few hundred μs to input write data 405 (e.g. a value calculated from the NH29W12811T datasheet is: cycle time 120 ns×2112 bytes=253.44 μs), which is extremely long compared with other command inputs and address inputs that require less than 1 μs.
In other words, time required for update is approximately equal to the total of erase busy 414, time required to input write data 405, and write busy 407.
As described above, when data is updated in the existing memory card 300, new data is written to an already erased physical block 322, and then a physical block 322 which has become old data due to such writing is erased. This is because, if new data were written to a physical block 322 that contains original data after such physical block 322 is erased, there would be the state in which the original data has already been erased and the new data has not yet been written, for example, when some abnormality occurred during data processing, which causes a possibility of data destruction from the viewpoint of the host apparatus.
However, when data is updated in the existing memory card 300, there is such a problem as the duplication of the same data from the standpoint of the host apparatus in which new data has already been written and a physical block 322 which became old data has not yet been erased, when some abnormality occurs in the stage where such new data has been written to an already erased physical block 322.
Furthermore, when data is updated in the existing memory card 300, there exists a period during which the next command cannot be inputted from the controller 310 to the flash memory 320 while erasure is ongoing. This causes time required for update to get longer.
Moreover, when the capacity of the memory card 300 becomes lager, the capacity of the address conversion table 313 and erase block table 3l14 also becomes larger, which further leads to an increased capacity of the RAM of the controller 310 in which these tables are generated.
The present invention has been conceived in view of the above circumstances, and it is an object of the present invention to provide a nonvolatile storage device and a control method thereof capable of maintaining data consistency even when some abnormality occurs while data is being updated, as well as capable of shortening the time required for updating data.